1. Field of the Invention
This invention generally relates to a circuit board structure and a fabrication method thereof, and more specifically, to a circuit board structure with an embedded semiconductor element and a fabrication method thereof.
2. Description of Related Art
As the electronic industry vigorously flourishes, designs of electronic products are trending toward low weight, small thickness, and small size, and the developing trend of product functions has been gradually towards high performance, high capability, and high speed. In order to meet the demand for high integration and miniaturization of semiconductor devices, the circuit board that provides a plurality of active/inactive elements and circuit carriers has evolved from double-layered board to multi-layered board, thus within a limited space, the available circuit area of circuit board can be expanded by means of interlayer connection to meet the demand for integrated circuits of high electronic density, and also the performance and capability of a single semiconductor package can be enhanced to keep up with the developing trend of electronic products of small size, high capability, and high speed.
The circuit board manufacturing industry is always pursuing the goal of low cost, high reliability, and high wiring density for its products. In order to reach the goal, a build-up technique has been developed, wherein a plurality of dielectric layers and circuit layers are alternately stacked on the surface of a core circuit board, and then a plurality of conductive structures, e.g. conductive vias, are formed in the dielectric layers for electrical connection with the circuit layers; in the process of circuit build-up, a difference in the coefficient of thermal expansion (CTE) causes uneven thermal stress, which in turn causes warpage and other problems, in order to avoid these problems, the circuit build-up is generally processed on both upper and lower surfaces of the core circuit board, thus to form a symmetrical build-up structure to prevent warpage.
However, based on practical demand of circuit design, the purposes of the upper and the lower surfaces of the core circuit board are different; therefore, the circuit layout of the upper surface of the core circuit board is frequently different from the circuit layout of the lower surface of the core circuit board, besides, the differences between the coefficient of thermal expansion of the metallic conductive layers and insulating layers and solder masks are great, when temperature changes in the fabrication process, situations of warpages happen frequently; in addition, when circuit density of one surface of the core circuit board is higher than the circuit density of the other surface, temperature changes that happen in processes of, e.g. baking, encapsulant curing, and thermal cycle, will generate different thermal stresses on the upper and the lower surfaces of the core circuit board, therefore, the two surfaces of the core circuit board will generate different degrees of deformation or shrinkage, in other words, warpage will happen to the core circuit board, in a more serious situation, delamination occurs between layers of the circuit board.
In addition, along with the wide development of portable products of communications, networks, computers, and others, semiconductor packages of ball grid array (BGA), flip chip, chip size package (CSP), multi chip module (MCM), and others that have features of high density of multi pins have become the mainstream of the semiconductor market. To meet the demand for high integration, sides of the circuit board for mounting semiconductor elements on must be fabricated to have matching multiple circuit layers of high density and fine circuit, oppositely, sides on the circuit board for mounting external electronic devices on does not have the same matching high wiring density as the sides for mounting chips, thus warpage is prone to happen, and also the semiconductor element embedded in the core circuit board is susceptible to damage due to uneven thermal stress.
Please refer to FIGS. 1A through 1E, which illustrate the steps of a fabrication process in mounting a semiconductor element on a core circuit board.
As shown in FIG. 1A, providing a core circuit board 11 having a first surface 11a and a second surface 11b, wherein the core circuit board 11 has a through hole 110 penetrating the core circuit board 11 from the first surface 11a to the second surface 11b, and then forming a de-molding membrane 12 on the second surface 11b of the core circuit board 11 to block one end of the through hole 110.
As shown in FIG. 1B, receiving a semiconductor element 13 in the through hole 110 of the core circuit board 11, wherein the semiconductor element 13 has an active surface 13a and an inactive surface 13b, the active surface 13a has a plurality of electrode pads 131, and the semiconductor element 13 is mounted on a surface of the de-molding membrane 12 inside the through hole 110 via the inactive surface 13b. 
As shown in FIG. 1C, filling the gap between the semiconductor element 13 and the through hole 110 of the core circuit board 11 with an adhesive 14, so as to secure the semiconductor element 13 to the through hole 110.
As shown in FIG. 1D, removing the de-molding membrane 12 from the second surface 11b of the core circuit board 11 and the inactive surface 13b of the semiconductor element 13.
As shown in FIG. 1E, forming a circuit build-up structure 15 on the first surface 11a of the core circuit board 11 and the active surface 13a of the semiconductor element 13; wherein the circuit build-up structure 15 comprises: at least one dielectric layer 151, a circuit layer 152 stacked on the dielectric layer 151, and a plurality of conductive structures 153 formed in the dielectric layer 151; wherein the conductive structures 153 are electrically connected to the electrode pads 131 of the semiconductor element 13, and a plurality of electrically connecting pads 154 are disposed on the outer surface of the circuit build-up structure 15; and forming a solder mask 16 on the outer surface of the circuit build-up structure 15, wherein the solder mask 16 has a plurality of openings 160 for exposing the electrically connecting pads 154 on the outer surface of the circuit build-up structure 15.
According to the above descriptions, based on the demands of circuit designs on the first surface 11a and the second surface 11b of the core circuit board 11, the circuit build-up structure 15 is formed only on the first surface 11a, and the coefficient of thermal expansion (CTE) of the circuit layers does not match the CTE of the dielectric layer. A difference in the coefficients of thermal expansion between different components of a semiconductor package generates thermal stress that, in turn, causes uneven thermal stress to the surfaces of the package structure, therefore, situations of warpage or delamination are prone to happen in the fabrication process and then indirectly affect reliability and quality of products. Besides, the number of circuit layers of the circuit build-up structure is limited by warpage; in other words, warpage renders a high level and a great number of circuit layers integration impossible and further prevents the development of semiconductor devices from high integration and miniaturization.
Hence, it is a highly urgent issue in the circuit board industry as to how to provide a circuit board structure that has an embedded semiconductor element, in order to overcome the aforementioned drawback regarding poor anti-flexural strength of a circuit board structure as found in the prior art.